Documentation
README
Interrupts and Exceptions (Bare-Metal)
Purpose
Guide agents through bare-metal interrupt handling on ARM Cortex-M: NVIC configuration, ISR writing rules, exception handlers (HardFault, BusFault), priority grouping, nesting, tail-chaining, and latency considerations.
When to Use
- Configuring peripheral IRQ priorities
- Writing ISRs that must not block
- Debugging HardFault after enabling interrupts
- Sharing data between ISR and main loop
- Optimizing interrupt latency
Workflow
1. NVIC overview (Cortex-M)
This is the opening of the README. Read the full README on GitHub.