Readable Verilog Generator is an AI Engineering skill for Claude Code, published by Eriemon in verilog-generator.
Readable Verilog Generator creates, reviews, annotates, repairs, and validates synthesizable Verilog-2001 RTL. Use it for readable module generation, existing-design analysis, semantic comments, testbench planning, and evidence-backed fixes.
Readable Verilog Generator is cataloged under AI Engineering on DirSkills. Readable Verilog Generator comes from a repository tagged agent-skill, claude-skills, codex-skills, deepseek-harness-skills and eda.
Documentation
Generate, analyze, improve, and verify readable Verilog-2001 RTL through the bundled runtime under scripts/python/. Keep design RTL and verification testbenches in .v files, use scripts/python/facade/verilog_api.py for host integration, and treat formatter-AST and external-tool evidence as stronger than model self-assessment.
This is the opening of the README. Read the full README on GitHub.
Readable Verilog Generator ranks #2276 by stars among the 2631 AI Engineering skills in this catalog. The most-starred ones next to it are Architecture Decision Records, AI-First Engineering and Agentic OS. DirSkills ranks by the star count of the repository each skill ships in, so that order reflects how popular those repositories are rather than any review of Readable Verilog Generator against them. Open each page to compare what they document and how they install.
Readable Verilog Generator is one of 2631 AI Engineering skills cataloged on DirSkills, ranked #2276 by stars among them.