Documentation
README
Detecting Design Errors (SLDV DED + Root Cause Analysis)
When to Use
- User asks to check a Simulink model for design errors (division-by-zero, overflow, dead logic, out-of-bounds)
- User asks to find root causes of DED findings
- User asks to fix or understand an analysis finding
- User asks why there is missing coverage due to dead logic (dead logic gates prevent coverage objectives from being satisfied)
- User has SLDV artifacts (
.matfile) and wants analysis without re-running DED
When NOT to Use
This is the opening of the README. Read the full README on GitHub.